With a view to achieving higher integration and higher performance of a semiconductor device, a vertical transistor SGT has been proposed which comprises a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see, for example, the following Patent Documents 1 and 2). In the SGT, a source, a gate and a drain are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor. In addition, the gate is formed to surround a channel region, so that, as a size of a pillar-shaped semiconductor layer is reduced, channel controllability of the gate can be effectively improved to obtain steep subthreshold characteristics. Furthermore, an improvement in carrier mobility based on electric field relaxation in the channel region can be expected by setting an impurity concentration and a size of the pillar-shaped semiconductor layer to allow the pillar-shaped semiconductor layer to become fully depleted. Therefore, the use of the SGT makes it possible to simultaneously achieve higher integration and higher performance as compared with the conventional planar transistor.
As methodology to form such an SGT, there have been primarily known the following two methods. The first SGT forming method is disclosed in the Patent Document 1, wherein it comprises: forming a pillar-shaped semiconductor layer by etching in advance; then forming a gate dielectric film and a gate conductive film on the pillar-shaped semiconductor layer by respective desired thicknesses; and forming a gate electrode by etching. The second SGT forming method is disclosed in the Patent Document 2, wherein it comprises: forming a gate conductive film in advance; then forming a contact hole to penetrate through the gate conductive film; and forming a gate dielectric film and a pillar-shaped semiconductor layer inside the contact hole. A conventional example using each of the above two methods will be described below, by taking, for the sake of simplicity, a structure and a production method for a semiconductor device comprising an inverter circuit with a simple configuration, as an example of a structure and a production method for a semiconductor device comprising a transistor-based circuit.
As a conventional example using the first method, an SGT disclosed in the Patent Document 1 will be first described.
FIG. 123(a), FIG. 123(b) and FIG. 123(c) show an equivalent circuit of a CMOS inverter designed using the SGT disclosed in the Patent Document 1, a layout of the CMOS inverter, and a structure of the CMOS inverter in cross-section taken along the cutting-plane line B-B′ in the layout diagram of FIG. 123(b), respectively. Referring to FIGS. 123(b) and 123(c), an N-well 1302 and a P-well 1303 are formed in an upper region of a Si substrate 1301. A pillar-shaped silicon layer 1305 forming a PMOS (PMOS-forming pillar-shaped silicon layer 1305) and a pillar-shaped silicon layer 1306 forming an NMOS (NMOS-forming pillar-shaped silicon layer 1306) are formed on a surface of the Si substrate, specifically on respective ones of the N-well region and the P-well region, and a gate 1308 is formed to surround the pillar-shaped silicon layers. Then, each of a P+ drain diffusion layer 1310 formed underneath a PMOS-forming pillar-shaped semiconductor, and a N+ drain diffusion layer 1312 formed underneath an NMOS-forming pillar-shaped semiconductor, is connected to an output terminal Vout 14. A source diffusion layer 1309 formed in an upper portion of the PMOS-forming pillar-shaped silicon layer is connected to a power supply potential Vcc 14, and a source diffusion layer 1311 formed in an upper portion of the NMOS-forming pillar-shaped silicon layer is connected to a ground potential Vss 14. Further, the gate 1308 common to the PMOS and the NMOS is connected to an input terminal Vin 14. In this manner, the CMOS inverter is formed.
In the above conventional example, the source, the gate and the drain are arranged in a vertical direction, so that an occupancy area of the transistor itself is less than that in the conventional planar transistor. However, element isolation is achieved based on a LOCOS (local oxidation of silicon) technique, and consequently an element isolation width is increased to cause deterioration in area efficiency in an integrated circuit and difficulty in fully taking advantage of the area reduction effect of the SGT. Moreover, in this SGT structure, it is necessary to reduce a resistance of the drain diffusion layer (1310, 1312), and, in cases where the drain diffusion layer (1310, 1312) is lined with a contact to reduce the resistance, the contact has to be formed on almost the entire region of a surface of the drain diffusion layer, which significantly restricts flexibility in laying lines in a first layer.
Secondly, an example of an NMOS sense amplifier of a DRAM using the SGT disclosed in the Patent Document 1 will be described below. FIG. 124(a), FIG. 124(b) and FIG. 124(c) are a diagrams showing an equivalent circuit of the NMOS sense amplifier, a top plan view showing a structure of the NMOS sense amplifier, and a sectional view taken along the cutting-plane line A-A′ in the top plan view of FIG. 124(b), respectively.
Referring to FIG. 124(a), a flip-flop is formed using an NMOS Qn 151 and an NMOS Qn 152, wherein the NMOS Qn 151 and the NMOS Qn 152 are connected to a bit-line BL and a bit-line BLB, respectively. Each of the Qn 151 and the Qn 152 is also connected to an NMOS Qn 153 for activating the sense amplifier, wherein a source of the Qn 153 is connected to a ground potential Vss 15.
Referring to FIGS. 124(b) and 124(c), a P-well 1322 is formed in an upper region of a Si substrate 1321, and a plurality of pillar-shaped silicon layers 1323 to 1328 are formed on a surface of the Si substrate. The Qn 151 which is one of two NMOSs constituting the sense amplifier, is formed by two (1327, 1328) of the pillar-shaped silicon layers, and the Qn 152 which is the other NMOS, is formed by two (1324, 1325) of the remaining pillar-shaped silicon layers. A gate dielectric film 1329 and a gate electrode 1330 are formed around an outer periphery of each of the pillar-shaped silicon layers. Further, an N-type source diffusion layer 1331 and an N-type drain diffusion layer 1332 are formed, respectively, beneath and in an upper portion of each of the pillar-shaped silicon layers. Each of the bit-line BL 1333 and the bit-line BLB 1334 paired together is connected to the N+ drain diffusion layers 1332 in the respective upper portions of the two pillar-shaped silicon layers of a corresponding one of the MOS transistors Qn 151, Qn 152, via polycrystalline silicon films (i.e., contacts) formed on the respective drain diffusion layers 1332. Further, the gate electrode 1330 of the transistor Qn 152 is extended to a top of the pillar-shaped silicon layer 1323 located on a left and obliquely upper side in the layout diagram of FIG. 124(b), and connected to the bit-line BL 1333 via a contact. The gate electrode 1330 of the transistor Qn 151 is extended to a top of the pillar-shaped silicon layer 1326 located on a right and obliquely lower side in the layout diagram of FIG. 124(b), and connected to the bit-line BLB 1334 via a contact.
Each of the two pillar-shaped silicon layers 1323, 1326 is not provided as an element forming the MOS transistor but as a seat for ensuring a bit-line contact during a process of connecting the bit-line to the gate electrode. The source diffusion layer 1331 formed underneath the pillar-shaped silicon layers is a common source node, and connected to the ground potential Vss 15 through a contact 1335. Further, although not illustrated, a PMOS sense amplifier comprising a PMOS is formed along the same bit-lines in the same structure and layout as those of the above NMOS sense amplifier.
In the above sense amplifier, considering that a length of a portion of the source diffusion layer 1331 extending between the contact 1335 connected to a ground line and an adjacent one of the transistors becomes longer, it is essential to allow the source diffusion layer 1331 to be lined with a contact. However, in the circuit having such a complicated layout, it is difficult to allow the source diffusion layer to be lined with a contact, and consequently a parasitic resistance of the source diffusion layer is increased to cause degradation in circuit performance.
FIGS. 125(a) to 125(f) show a schematic process flow for forming a pillar-shaped silicon layer and a gate electrode, in the above conventional examples of SGTs. This process flow will be described below. In FIG. 125(a), a pillar-shaped silicon layer 1401 is formed on a silicon substrate by etching. In FIG. 125(b), a gate dielectric film 1402 is formed. In FIG. 125(c), a gate conductive film 1403 is formed. In FIG. 125(d), a gate-line resist (resist for a gate line) 1404 is formed to be in contact with a portion of a gate conductive film surrounding the pillar-shaped silicon layer. In FIG. 125(e), a gate etch process is performed. Through this process, a gate electrode and a gate line 1405 of an SGT are formed. In FIG. 125(f), the resist is released.
In this SGT forming method, the resist 1404 must be formed to be accurately in contact with the portion of the gate conductive film around a sidewall of the pillar-shaped silicon layer. Therefore, a process margin for forming the gate line is narrow, which causes difficulty in ensuring stable production. The following description will be made in regard to this point.
FIGS. 126 (a) to 126(f) illustrate a process flow in case where the gate-line resist 1404 is positionally deviated to the right side in FIG. 125(d). FIG. 126(d) shows a state after the resist is positionally deviated to the right side during alignment of a lithographic exposure. In this state, there arises a space between a resist 1414 and a sidewall of a pillar-shaped silicon layer 1411. In FIG. 126(e), a gate etch process performed. In FIG. 126(f), the resist is released. In this case, a gate electrode 1413 and a gate line 1415 of a resulting SGT are undesirably disconnected from each other.
FIGS. 127 (a) to 127(f) illustrate a process flow in case where the gate-line resist 1404 is positionally deviated to the left side in FIG. 125(d). FIG. 127(d) shows a state after the resist is positionally deviated to the left side during alignment of a lithographic exposure. In this state, there arises an overlapped area 1426 between a resist 1424 and a portion of a gate electrode on a top of a pillar-shaped silicon layer 1421. In FIG. 127(e), a gate etch process performed. In FIG. 127(f), the resist is released. In this case, a gate electrode 1423 of a resulting SGT undesirably has a shape abnormality 1427 on a side where the resist is formed.
The above positional deviation of the resist arising from the alignment inevitably occurs depending on a type of pattern and/or a position on a wafer. Thus, in this SGT forming method, a process margin for forming the gate line becomes extremely narrow.
Thirdly, as a conventional example using the second method, an SGT disclosed in the Patent Document 2 will be described below.
FIGS. 128(a) to 128(e) show respective cross-sectional structures of a plurality of types of CMOS inverters designed using the SGT disclosed in the Patent Document 2. As shown in FIG. 128(a), an N-well 1502 and a P-well 1501 are formed in an upper region of a Si substrate. A P+ diffusion layer 1504 and an N+ diffusion layer 1503 are formed on a surface of the Si substrate, specifically on respective ones of the N-well region and the P-well region. The P+ diffusion layer 1504 and the N+ diffusion layer 1503 are isolated from each other by a LOCOS film 1505. A PMOS-forming pillar-shaped silicon layer 1510 and an NMOS-forming pillar-shaped silicon layer 1509 are formed on respective ones of the P+ diffusion layer 1504 and the N+ diffusion layer 1503, and a gate 1506 is formed to surround the pillar-shaped silicon layers. Although not illustrated, the diffusion layer 1504 beneath the PMOS-forming pillar-shaped silicon layer, the diffusion layer 1503 beneath the NMOS-forming pillar-shaped silicon layer, and the gate electrode 1506, are connected to a power supply potential, a ground potential, and an input potential, respectively. Further, a diffusion layer (1512, 1511) formed in an upper portion of each of the PMOS-forming and NMOS-forming pillar-shaped silicon layers is connected to a line layer 1513 which is connected to an output potential.
In the SGT having the structure illustrated in FIG. 128(a), element isolation is performed using a LOCOS technique, in the same manner as that in the SGT structure disclosed in the Patent Document 1. Therefore, an element isolation width is increased to cause deterioration in area efficiency in an integrated circuit, and difficulty in fully taking advantage of the area reduction effect of the SGT.
FIG. 128(b) shows a conventional example in which an inverter is formed based on the same structure as that illustrated in FIG. 128(a). In FIG. 128(b), two diffusion layers 1531, 1532 formed in respective upper portions of the NMOS-forming and PMOS-forming pillar-shaped silicon layers are connected to each other through a silicide layer 1533, and further connected to a line layer 1534 via a contact formed on the silicide layer 1533.
In this structure, the two diffusion layers in the respective upper portions of the NMOS-forming and PMOS-forming pillar-shaped silicon layers are connected to each other through the silicide layer 1533. This makes it possible to facilitate layout of the line layer. However, an area of the inverter cannot be reduced as compared with that in FIG. 128(a), because it is determined by a total area of a diffusion layer (1523, 1524) beneath the pillar-shaped silicon layers, and an element isolation 1525. Moreover, the number of production processes is increased due to a need for adding a production process to form and pattern the silicide layer. Furthermore, in both the inverters illustrated in FIGS. 128(a) and 128(b), a parasitic resistance of the source diffusion layer is increased to cause degradation in circuit performance, as with the SGT disclosed in the Patent Document 1.
Two inverters illustrated in FIGS. 128(c) and 128(d) are structurally different from those in FIGS. 128(a) and 128(b). Thus, the difference will be described below, primarily by taking the inverter illustrated in FIG. 128(c) as an example.
Referring to FIG. 128(c), a P-well 1541 is formed in a Si substrate. An N+ diffusion layer 1542 is formed on a surface of the Si substrate, and a silicide layer 1543 is formed on a surface of the N+ diffusion layer. Further, each of the N+ diffusion layer 1542 and the silicide layer 1543 is isolated by a LOCOS film 1551. A PMOS-forming pillar-shaped silicon layer 1548 and an NMOS-forming pillar-shaped silicon layer 1547 are formed on the silicide layer 1543, and a gate 1544 is formed to surround the pillar-shaped silicon layers. Although not illustrated, the silicide layer 1543, the gate electrode 1544, a diffusion layer 1550 formed in an upper portion of the PMOS-forming pillar-shaped silicon layer, and a diffusion layer 1549 formed in an upper portion of the NMOS-forming pillar-shaped silicon layer, are connected to an output potential, an input potential, a power supply potential, and a ground potential, respectively. Thus, differently from the inverters illustrated in FIGS. 128(a) and 128(b), in this inverter, an output potential is output on the side of the substrate.
The inverter in FIG. 128(c) designed to output an output potential on the side of the substrate can employ a structure where and a P+ diffusion layer 1546 formed in a bottom portion of the pillar-shaped silicon layer 1548 and an N+ diffusion layer 1545 formed in a bottom portion of the pillar-shaped silicon layer 1547 are connected to each other through the silicide layer 1543. This structure is free of a need for element isolation to isolate between the P+ diffusion layer 1546 and the N+ diffusion layer 1545, and therefore an occupancy area of this inverter becomes reduced as compared with those of the inverters illustrated in FIGS. 128(a) and 128(b).
However, in this structure, a transistor must be formed after forming the silicide layer 1543 underneath the pillar-shaped silicon layer. Generally, a silicide layer is low in thermal resistance. In particular, nickel silicide (NiSi) employed in nano-devices since the 65-nm generation has an upper temperature limit of about 500 to 600° C. Thus, when the silicide layer is affected by an impurity activation heat treatment to be performed at about 1000° C. during transistor formation, an excessive reaction undesirably occurs therein to cause an increase in resistance and leak current. In view of this, it is practically difficulty to ensure stable production based on the structure of this conventional example. Moreover, due to the silicide layer 1543 located underneath the pillar-shaped silicon layer, silicon cannot be formed by epitaxial growth during crystal growth of the pillar-shaped silicon layer, to cause significant deterioration in transistor characteristics.
A conventional example illustrated in FIG. 128(d) is configured to generate an output potential on the side of a substrate, as with the inverter illustrated in FIG. 128(c). In this conventional example, a silicide layer 1563 is formed along an interface between a P+ diffusion layer 1566 formed in a bottom portion of a pillar-shaped silicon layer 1568 and an N+ diffusion layer 1562 on a Si substrate, to connect the P+ diffusion layer 1566 to an N+ diffusion layer 1565 formed in a bottom portion of an NMOS-forming pillar-shaped silicon layer 1567, and the N+ diffusion layer 1562 on the substrate. Thus, this structure is free of a need for element isolation to isolate between the N+ diffusion layer and the P+ diffusion layer, and therefore an inverter occupancy area becomes reduced. However, in this conventional example, a transistor is formed after forming the silicide layer, in the same manner as that in the conventional example illustrated in FIG. 128(b), and, due to the problem with the thermal resistance of the silicide layer, it is difficult to ensure stable production. Moreover, due to the silicide layer 1563 located underneath the PMOS-forming pillar-shaped silicon layer, silicon cannot be formed by epitaxial growth during crystal growth of the PMOS-forming pillar-shaped silicon layer, to cause significant deterioration in transistor characteristics.
FIG. 128(e) shows a conventional example disclosed in the following Non-Patent Document 1 which describes an SGT inverter formed on an SOI substrate using the same production methods as those in FIGS. 128(a) to 128(d). In this conventional example, an inverter is formed on an SOI substrate. This eliminates a need for forming a well, and allows an element isolation width to be reduced, so that an occupancy area of the inverter can be reduced by just a reduction in element isolation width, as compared with those of the inverters having similar structures as illustrated in FIGS. 128(a) and 128(b).
This inverter will be specifically described below. As shown in FIG. 128(e), an N+ source diffusion layer 1572 and a P+ source diffusion layer 1573 are formed on a buried oxide film 1571. An NMOS-forming pillar-shaped silicon layer 1574 is formed on the N+ source diffusion layer 1572, and a PMOS-forming pillar-shaped silicon layer 1575 is formed on the P+ source diffusion layer. Further, an N+ drain diffusion layer 1576 is formed in an upper portion of the NMOS-forming pillar-shaped silicon layer 1574, and a P+ drain diffusion layer 1577 is formed in an upper portion of the PMOS-forming pillar-shaped silicon layer 1575. A gate 1578 is formed around the pillar-shaped silicon layers. The N+ source diffusion layer 1572 is connected to a ground potential via a contact extending from a line layer 1579, and the P+ source diffusion layer 1573 is connected to a power supply potential via a contact extending from a line layer 1580. The diffusion layer (1576, 1577) in the upper portion of each of the NMOS-forming and PMOS-forming pillar-shaped silicon layers is connected to an output potential via a contact extending from a line layer 1581.
In this conventional example, an output potential is formed on the side of the lines, as with the inverters illustrated in FIGS. 128(a) and 128(b), and therefore there is a need for element isolation on the side of the substrate. However, this inverter using an SOI substrate is free of the need for forming a well, so that a required element isolation width can be achieved simply by isolating between the source diffusion layers 1572, 1573 through etching. This makes it possible to reduce an occupancy area by just a reduction in element isolation width, as compared with the inverters using a LOCOS technique for element isolation as illustrated in FIGS. 128(a) and 128(b). Nevertheless, this conventional example also involves a problem of a relatively large parasitic resistance in the source diffusion layer, causing degradation in circuit performance.
As above, all the inverters illustrated in FIGS. 128(a) to 128(e) are incapable of avoiding deterioration in circuit performance due to a parasitic resistance of the source diffusion layer.
FIGS. 129(a) to 129(e) show a schematic process flow for forming a pillar-shaped silicon layer and a gate electrode, in the SGTs illustrated in FIGS. 128(a) to 128(e). This process flow will be described below.
In FIG. 129(a), a silicon oxide film 1601, a gate conductive material 1602 and a silicon oxide film 1603 are formed on a silicon substrate in this order. In FIG. 129(b), a contact hole 1604 is formed to penetrate through the silicon oxide film 1603, the gate conductive material 1602 and the silicon oxide film 1601. In FIG. 129(c), a gate dielectric film 1605 is formed on an inner wall of the contact hole. In FIG. 129(d), a silicon film is formed inside the contact hole by epitaxial growth, to form a pillar-shaped silicon layer 1606. In FIG. 129(e), an upper portion of the pillar-shaped silicon layer is isolated.
In this SGT forming method, if the contact hole for forming the pillar-shaped silicon layer, and a gate line pattern, are formed by a single lithography process, gate patterning becomes complicated, and it is significant difficult to form a gate electrode of an SGT to have a sufficiently small film thickness. Thus, an area to be occupied by the gate electrode is increased. Otherwise, if the contact hole for forming the pillar-shaped silicon layer, and the gate line pattern, are formed by separate lithography processes, an area to be occupied by the gate electrode surrounding the pillar-shaped silicon layer must be formed to have an unnecessarily large size, in consideration of positional mismatching and dimensional error between the two processes. Consequently, in either case, an area occupied by the gate electrode becomes greater than an actually required area to cause an increase in circuit occupancy area.
The following point can be pointed out as a major difference between the above two SGT forming methods.
In the first method, the pillar-shaped silicon layer is formed by etching a single-crystal silicon substrate, so that a defect and irregularities in a channel region arising from etching or the like can be easily recovered by performing a surface treatment, such as sacrificial oxidation or hydrogen annealing (see the following Non-Patent Document 2). Thus, a high carrier mobility can be achieved in the channel region to facilitate obtaining high-performance transistor characteristics.
Differently, in the second method, the pillar-shaped silicon layer is formed of silicon epitaxially grown inside the contact hole. Generally, a sidewall of the contact hole has irregularities occurring during etching, and it is difficult to eliminate such irregularities. Consequently, the irregularities are transferred to a surface of a channel region formed in the sidewall of the contact hole to cause deterioration in carrier mobility and difficulty in forming a high-performance transistor. Moreover, considering that a size of the contact hole in currently produced LSIs in the 65-nm generation is about 80 nm, and the contact hole will become finer and finer in the future, it is difficult to form an epitaxial silicon film from the side of a bottom of such a fine contact hole, in adequate yield.    Patent Document 1: JP 2-188966A    Patent Document 2: JP 7-99311A    Non-Patent Document 1: S. Maeda, et al., “Impact of a Vertical φ-Shape Transistor Cell for 1 Gbit DRAM and Beyond”, IEEE TRANSACTIONS ON ELECTRON DEVICES, December 1995, VOL. 42, NO. 12, pp. 2117-2124    Non-Patent Document 2: Y.-K Choi, et al., “FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering”, International Electron Devices Meeting Technical Digest, 2002, p. 259
Thus, in terms of achieving an SGT capable of high integration and high performance and producible in high yield, the SGT structure and forming method based on the first method is superior to the SGT structure and forming method based on the second method. However, the SGT structure and forming method based on the first method has the following problems.
Firstly, there remains a need for achieving a reduction in area of each element, and element isolation excellent in area efficiency, to reduce a circuit occupancy area. Secondly, there remains a need for reducing a parasitic capacitance and a parasitic resistance of a source/drain region to improve transistor performance Thirdly, there remains a need for achieving a gate-line forming process having a wide process margin.